module Multi_Register_file(
	iClk,
	iWriteENB,		// Enable write at ENB == 1
	iReadAddr1,		// Register address to Read 1
	iReadAddr2,		// Register address to Read 2
	iWriteAddr,		// Register address to Write
	iWriteData,		// Data to Write
	oReadData1,		// Data getting out
	oReadData2		// Data getting out
	);

	input iClk, iWriteENB;
	input [4:0] iReadAddr1, iReadAddr2, iWriteAddr;
	input [7:0] iWriteData;

	output [7:0] oReadData1, oReadData2;

	reg [7:0] regFile [31:0];

	always @(posedge iClk)
		begin
			if(iWriteENB) regFile[iWriteAddr] <= iWriteData;
		end
	
	assign oReadData1 = (iReadAddr1 == 5'd0)? 8'd0:regFile[iReadAddr1]; // 8'd0 ????? hardwired 0
	assign oReadData2 = (iReadAddr2 == 5'd0)? 8'd0:regFile[iReadAddr2]; // 8'd0 ????? hardwired 0

endmodule

